Field of Invention
This invention relates to data buffers of the type referred to as First-In, First-Out (FIFO) buffer memories; and more particularly to such buffers in which input and output data read and write operations are independent and asynchronously operated.
Many commercially-available data buffers are configured using dual-port memory cells in a random-access array with asynchronous read and write capabilities per cell. The configuration of such cells within a Random Access Memory structure (RAM) requires addressing schemes including pointers that indicate the location to be written into and the location to be read from in sequential order. Such RAM FIFO buffers also require one or more a test or flat bits to designate which written words in memory have not yet been read out. Also, the status of pointers has to be detected to assure that data can only be written into empty memory locations, and that data can only be read out from occupied memory locations.
Conventional FIFO buffers usually designate the status of the FIFO buffer as being full or empty or partially full in order to help resolve ambiguities in detected pointer conditions, and usually also include comparators and control logic to prevent over-run or under-run conditions as data is written in and read out.
Conventional FIFO buffers may be expanded in data word length and in number of words stored by cascading several similar circuits and by using `handshaking` control techniques that transfer from one circuit to the next in the cascaded array. These expansions commonly introduce undesirable delays in the time required to access stored data, and generally contribute to the complexity of the required control logic.